1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device having an open bit line structure and a semiconductor memory system including the same.
2. Description of the Related Art
In general, a semiconductor memory device such s a double data rater synchronous dynamic random access memory (DDR SDRAM) includes a memory bank for storing large amounts of data. The memory bank is an aggregation of a plurality of unit memory cells that store data. Each of the unit memory cells is coupled to a corresponding bit line for transferring data in units of a bit. A bank structure of the semiconductor memory device is classified into a folded bit line structure and an open bit line structure, according to a structure in which a bit line is disposed.
In the folded bit line structure, a data bit line and a reference bit line are disposed in the same memory cell mat according to a sense amplifier which is disposed in a memory area of the semiconductor memory device. The cell mat denotes a unit of memory mats included in a memory bank of a semiconductor memory device. The data bit line is a bit line in which a data stored in a memory cell is substantially transferred, and the reference bit line is a bit line having a reference value which is compared with a value of the data transferred from the data bit line. In the open bit line structure, a data bit line and a reference bit line are disposed in a different memory cell mat according to a sense amplifier.
As described above, since the folded bit line structure has the data bit line and the reference bit line disposed in the same memory cell mat, the same noises are reflected on the data bit line and the reference bit line. Accordingly, the noise reflected on the data bit line and the noise reflected on the reference bit line cancel each other out, and thus the folded bit line structure has an excellent characteristic for noise cancellation in comparison with the open bit line structure.
Since the open bit line structure has the data bit line and the reference bit line disposed in the different memory cell mat, the noise reflected on the data bit line is different from the noise reflected on the reference bit line. Accordingly, the open bit line structure has a poor characteristic for noise cancellation in comparison with the folded bit line structure.
Furthermore, an area of a unit memory cell in the folded bit line structure is different from that in the open bit line structure. The unit memory cell in the folded bit line structure is designed to have 8F2 while the unit memory cell in the open bit line structure is designed to have 6F2. This means that a memory bank having an open bit line structure may be designed to occupy an area smaller than a memory bank having a folded bit line structure when the same number of data is stored. That is, in a view of area the open bit line structure is more beneficial than the folded bit line structure.
FIG. 1 is a block diagram illustrating a typical semiconductor memory device having an open bit line structure. For reference, FIG. 1 shows a configuration corresponding to one unit memory bank which includes memory cell mats corresponding to a pair of local data lines LIO and LIOB and sense amplifiers.
Referring to FIG. 1, the semiconductor memory device has a plurality of memory cell mats 110, 130, 150, . . . , 160 and 180, and a plurality of sense amplifiers 120, 140, . . . , and 170. A unit memory bank composed of 64 memory cell mats is described as an example. The semiconductor memory device is composed of first to 64th memory cell mats 110, 130, 150, . . . , 160 and 180, and first and 63th sense amplifiers 120, 140, . . . , and 170 are disposed therebetween.
When the semiconductor memory device has the open bit line structure, each sense amplifier receives a data of a data bit line from one of two adjacent memory cell mats and a data of a reference bit line from the other of two adjacent memory cell mats, and amplifies the data of the data bit line and the data of the reference bit line. Each sense amplifier outputs an amplification result to the pair of local data lines LIO and LIOB in response to a column selection signal YI. For reference, the above described operation corresponds to a typical read operation. In a write operation, data loaded on the pair of local data lines LIO and LIOB are transferred to the respective memory cell mats in response to the column selection signal YI, and stored therein.
Hereinafter, a simple write operation will be described in detail. For convenience of description, it is assumed that a second write operation of the second memory cell mat 130 is consecutively performed after a first write operation of the first memory cell mat 110 has been performed.
During the first write operation of the first memory cell mat 110, a first word line WL1 corresponding to the first memory cell mat 110 is activated. Then, data to be stored in the first memory cell mat 110 are transferred to the first sense amplifier 120 through the pair of local data lines LIO and LIOB, and amplified and stored in the first memory cell mat 110 through the first sense amplifier 120. In detail, the first sense amplifier 120 selectively couples the pair of local data lines LIO and LIOB to a data bit line (not shown) disposed in the first memory cell mat 110 and a reference bit line (not shown) disposed in the second memory cell mat 130 in response to the column selection signal YI. Accordingly, the data transferred from the pair of local data lines LIO and LIOB are stored in the first memory cell mat 110 through the data bit line.
Subsequently, during the second write operation of the second memory cell mat 130, a second word line WL2 corresponding to the second memory cell mat 130 is activated. Then, data to be stored in the second memory cell mat 130 are transferred to the first sense amplifier 120 through the pair of local data lines LIO and LIOB, and amplified and stored in the second memory cell mat 130 through the first sense amplifier 120.
The semiconductor memory device is generally designed to operate according to a preset specification (SPEC.). In such a preset specification, a write recovery time ‘tWR’ is defined as a time until a precharge command is applied after data are applied according to a write operation. The write recovery time ‘tWR’ is used as a reference for determining an interval between two consecutive write commands.
In the above write operations as described the second write operation of the second memory cell mat 130 is performed after the first write operation of the first memory cell mat 110 is performed. However, after the first write operation of the first memory cell mat 110 is performed, a precharge operation is substantially performed before the second write operation of the second memory cell mat 130 is performed. The write recovery time ‘tWR’ is a time until a precharge command for the precharge operation is applied, after data are applied according to the first write operation of the first memory cell mat 110.
FIG. 2 is a timing diagram illustrating the write recovery time ‘tWR’.
Referring to FIGS. 1 and 2, the first write operation of the first memory cell mat 110 and the second write operation of the second memory cell mat 130 are described in detail.
As illustrated in FIGS. 1 and 2, an external controller (not shown) sends an active command ACT #1 and a write command WT for the first write operation of the first memory cell mat 110 to the semiconductor memory device, and transmits data DAT to be written in the first memory cell mat 110. The data DAT are transferred and stored in the first memory cell mat 110 through the pair of local data lines LIO and LIOB.
The data bit line and the reference bit line of the first and second memory cell mats 110 and 130 are precharged to a given voltage level in response to a precharge command PCG. The write recovery time ‘tWR’ may be defined as a time until the precharge command PCG is applied, after the data DAT are inputted according to the first write operation of the first memory cell mat 110. The second write operation of the second memory cell mat 130 may be performed after the data bit line and the reference bit line of the first and second memory cell mats 110 and 130 are precharged. That is, the second write operation of the second memory cell mat 130 may be performed at least when the write recovery time ‘tWR’ is available after the first write operation of the first memory cell mat 110 has been performed.
Following the first write operation of the first memory cell mat 110 being performed, the second write operation of the second memory cell mat 130 is performed after the write recovery time ‘tWR’ from the first write operation of the first memory cell mat 110. Such a write operation may be applied to all memory cell mats. That is, in case of a semiconductor memory device having an open bit line structure, at least a time corresponding to the write recovery time ‘tWR’ has to be available between consecutive write operations when the consecutive write operations are performed on adjacent memory cell mats included in a unit memory bank.